RTL-BenchLS - Round-Trip NL Spec (r=0.5): leaderboard

Round-trip reasoning on 420 designs: the model compresses a Verilog design into a natural-language specification at most half the design length, then regenerates the RTL from its own specification, from RTL-BenchLS (2026), a benchmark of formally verified Verilog designs; the score is the functional pass rate in percent, where output must be formally equivalent to the golden design (Cadence LEC or SEC), and higher is better.

Metric: Functional pass rate (%) on round-trip reasoning on 420 designs (slice 1 of RTL-BenchLS): the model compresses a Verilog design into an intermediate abstract, then regenerates the RTL from its own abstract, the abstract a natural-language specification at most 0.5 times the design length; functional pass rate (%; output formally equivalent to the golden design, Cadence Conformal LEC for combinational and JasperGold SEC for sequential designs), temperature 0.2; higher is better. Source: arxiv.org. Saturation forecast: Around 2029. 8 models tracked.

Top models

#ModelScoreOverall rank
1Claude Sonnet 4.517.1#250
2GPT-4o11.7#741
3Claude Haiku 4.511.7#568
4GPT-4o Mini11.3#1623
5DeepSeek V3.210.3#406
6Qwen 3.5 397B A17B4.6#246
7Llama 3.3 70B Instruct1.9#1357

No result here: #1 Claude Fable 5.2, #2 Gemini 4 Carbon, #5 Claude Opus 5.5.

Interactive version: theaggregate.ai/benchmark?slug=rtl-benchls-round-trip-nl-spec-r-0-5 · How It Works · Data refreshed daily, snapshot 2026-11-13.