RTL-BenchLS - Round-Trip Diagram Spec: leaderboard
Round-trip reasoning on 420 designs: the model rewrites a Verilog design as a diagram-style specification (state tables, truth tables, block descriptions), then regenerates the RTL from it, from RTL-BenchLS (2026), a benchmark of formally verified Verilog designs; the score is the functional pass rate in percent, where output must be formally equivalent to the golden design (Cadence LEC or SEC), and higher is better.
Metric: Functional pass rate (%) on round-trip reasoning on 420 designs (slice 1 of RTL-BenchLS): the model compresses a Verilog design into an intermediate abstract, then regenerates the RTL from its own abstract, the abstract a diagram-style natural-language specification (state tables, truth tables, block descriptions); functional pass rate (%; output formally equivalent to the golden design, Cadence Conformal LEC for combinational and JasperGold SEC for sequential designs), temperature 0.2; higher is better. Source: arxiv.org. Saturation forecast: Around September 2027. 8 models tracked.
Top models
| # | Model | Score | Overall rank |
|---|---|---|---|
| 1 | Claude Sonnet 4.5 | 39.5 | #250 |
| 2 | Claude Haiku 4.5 | 30.3 | #568 |
| 3 | GPT-4o | 24.6 | #741 |
| 4 | GPT-4o Mini | 18 | #1623 |
| 5 | DeepSeek V3.2 | 16.4 | #406 |
| 6 | Qwen 3.5 397B A17B | 3.7 | #246 |
| 7 | Llama 3.3 70B Instruct | 3.3 | #1357 |
No result here: #1 Claude Fable 5.2, #2 Gemini 4 Carbon, #5 Claude Opus 5.5.
Interactive version: theaggregate.ai/benchmark?slug=rtl-benchls-round-trip-diagram-spec · How It Works · Data refreshed daily, snapshot 2026-11-13.