RTL-BenchLS - Round-Trip C: leaderboard
Round-trip reasoning on 420 designs: the model translates a Verilog design into executable C, then regenerates the RTL from its own C code, from RTL-BenchLS (2026), a benchmark of formally verified Verilog designs; the score is the functional pass rate in percent, where output must be formally equivalent to the golden design (Cadence LEC or SEC), and higher is better.
Metric: Functional pass rate (%) on round-trip reasoning on 420 designs (slice 1 of RTL-BenchLS): the model compresses a Verilog design into an intermediate abstract, then regenerates the RTL from its own abstract, the abstract executable C code; functional pass rate (%; output formally equivalent to the golden design, Cadence Conformal LEC for combinational and JasperGold SEC for sequential designs), temperature 0.2; higher is better. Source: arxiv.org. Saturation forecast: Around July 2027. 8 models tracked.
Top models
| # | Model | Score | Overall rank |
|---|---|---|---|
| 1 | Claude Sonnet 4.5 | 39.5 | #250 |
| 2 | GPT-4o | 37.9 | #741 |
| 3 | DeepSeek V3.2 | 33.8 | #406 |
| 4 | Qwen 3.5 397B A17B | 28.3 | #246 |
| 5 | Claude Haiku 4.5 | 26.4 | #568 |
| 6 | GPT-4o Mini | 21.2 | #1623 |
| 7 | Llama 3.3 70B Instruct | 19.8 | #1357 |
No result here: #1 Claude Fable 5.2, #2 Gemini 4 Carbon, #5 Claude Opus 5.5.
Interactive version: theaggregate.ai/benchmark?slug=rtl-benchls-round-trip-c · How It Works · Data refreshed daily, snapshot 2026-11-13.