HierSVA-B - Vacuity Rate: leaderboard

HierSVA-B (2026) benchmarks LLM-generated SystemVerilog assertions for hierarchical hardware formal verification on 342 BaseJump STL modules, checked by formal proof with a commercial tool. This board is the share of generated assertions, in percent, that pass only vacuously; lower is better.

Metric: Vacuous proof rate (%, C2-V): share of generated assertions in evaluable runs that pass only vacuously on HierSVA-DS (342 hierarchical BaseJump STL modules, depths 0 to 9): static generation of SystemVerilog Assertions from RTL and submodule contracts, checked by formal proof in VC Formal; one run, reasoning enabled, temperature 0, strict JSON output; lower is better. Source: arxiv.org. Saturation forecast: Estimated already saturated. 12 models tracked.

Top models

#ModelScoreOverall rank
1Qwen 3.6 Max (Preview) (Thinking)0.1
2Kimi K2.60.2#178
3GPT-5.50.5#49
4GLM-5.11.3#179
5Qwen 3.6 Plus (Thinking)1.4#222 (Qwen 3.6 Plus)
6Gemini 3.1 Pro (Preview)1.5#94
7Claude Opus 4.7 (Thinking)1.8#79 (Claude Opus 4.7)
8GPT-5 Mini2.1#348
9Claude Haiku 4.5 (Thinking)6.5#568 (Claude Haiku 4.5)
10MiniMax-M2.715.4#518

No result here: #1 Claude Fable 5.2, #2 Gemini 4 Carbon, #5 Claude Opus 5.5.

Interactive version: theaggregate.ai/benchmark?slug=hiersva-b-vacuity-rate · How It Works · Data refreshed daily, snapshot 2026-11-13.