HierSVA-B - Proof Success: leaderboard

HierSVA-B (2026) benchmarks LLM-generated SystemVerilog assertions for hierarchical hardware formal verification on 342 BaseJump STL modules, checked by formal proof with a commercial tool. This board is the share of generated assertions, in percent, that are proven non-vacuously; higher is better.

Metric: Assertion proof success rate (%, C2-P): share of generated assertions in evaluable runs that are proven non-vacuously on HierSVA-DS (342 hierarchical BaseJump STL modules, depths 0 to 9): static generation of SystemVerilog Assertions from RTL and submodule contracts, checked by formal proof in VC Formal; one run, reasoning enabled, temperature 0, strict JSON output. Source: arxiv.org. Saturation forecast: Estimated already saturated. 12 models tracked.

Top models

#ModelScoreOverall rank
1Qwen 3.6 Max (Preview) (Thinking)95.2
2GLM-5.191#179
3Gemini 3.1 Pro (Preview)90.3#94
4Claude Opus 4.7 (Thinking)87.5#79 (Claude Opus 4.7)
5Kimi K2.686.2#178
6GPT-5 Mini77.9#348
7Qwen 3.6 Plus (Thinking)76.9#222 (Qwen 3.6 Plus)
8GPT-5.576.8#49
9Claude Haiku 4.5 (Thinking)74#568 (Claude Haiku 4.5)
10MiniMax-M2.758.2#518

No result here: #1 Claude Fable 5.2, #2 Gemini 4 Carbon, #5 Claude Opus 5.5.

Interactive version: theaggregate.ai/benchmark?slug=hiersva-b-proof-success · How It Works · Data refreshed daily, snapshot 2026-11-13.