HierSVA-B - Mutation Coverage: leaderboard

HierSVA-B (2026) benchmarks LLM-generated SystemVerilog assertions for hierarchical hardware formal verification on 342 BaseJump STL modules, checked by formal proof with a commercial tool. This board is the share of injected RTL faults, in percent, that the generated assertions detect; higher is better.

Metric: Mutation coverage (%, C4): share of eligible injected RTL faults that the generated assertion set detects on HierSVA-DS (342 hierarchical BaseJump STL modules, depths 0 to 9): static generation of SystemVerilog Assertions from RTL and submodule contracts, checked by formal proof in VC Formal; one run, reasoning enabled, temperature 0, strict JSON output. Source: arxiv.org. Saturation forecast: Around February 2027. 12 models tracked.

Top models

#ModelScoreOverall rank
1Kimi K2.689#178
2GPT-5.584.5#49
3GLM-5.178.1#179
4Gemini 3.1 Pro (Preview)74.7#94
5Claude Opus 4.7 (Thinking)70.5#79 (Claude Opus 4.7)
6Qwen 3.6 Max (Preview) (Thinking)70.4
7Qwen 3.6 Plus (Thinking)64.9#222 (Qwen 3.6 Plus)
8Claude Haiku 4.5 (Thinking)58.4#568 (Claude Haiku 4.5)
9GPT-5 Mini56.7#348
10MiniMax-M2.737.8#518

No result here: #1 Claude Fable 5.2, #2 Gemini 4 Carbon, #5 Claude Opus 5.5.

Interactive version: theaggregate.ai/benchmark?slug=hiersva-b-mutation-coverage · How It Works · Data refreshed daily, snapshot 2026-11-13.