HierSVA-B - Formal Core Coverage: leaderboard

HierSVA-B (2026) benchmarks LLM-generated SystemVerilog assertions for hierarchical hardware formal verification on 342 BaseJump STL modules, checked by formal proof with a commercial tool. This board is the coverage, in percent, of the statements and signals in the formal core of each design by the proven assertions; higher is better.

Metric: Formal core coverage (%, C5): union coverage of the design statements and signals in the formal core by the proven assertions on HierSVA-DS (342 hierarchical BaseJump STL modules, depths 0 to 9): static generation of SystemVerilog Assertions from RTL and submodule contracts, checked by formal proof in VC Formal; one run, reasoning enabled, temperature 0, strict JSON output. Source: arxiv.org. Saturation forecast: Around April 2027. 12 models tracked.

Top models

#ModelScoreOverall rank
1Kimi K2.653.3#178
2GPT-5.551.4#49
3GLM-5.143.3#179
4Qwen 3.6 Max (Preview) (Thinking)37.7
5Claude Opus 4.7 (Thinking)34.7#79 (Claude Opus 4.7)
6Gemini 3.1 Pro (Preview)33.8#94
7Claude Haiku 4.5 (Thinking)33.1#568 (Claude Haiku 4.5)
8Qwen 3.6 Plus (Thinking)29.4#222 (Qwen 3.6 Plus)
9MiniMax-M2.726.5#518
10GPT-5 Mini14.5#348

No result here: #1 Claude Fable 5.2, #2 Gemini 4 Carbon, #5 Claude Opus 5.5.

Interactive version: theaggregate.ai/benchmark?slug=hiersva-b-formal-core-coverage · How It Works · Data refreshed daily, snapshot 2026-11-13.