HierSVA-B - Formal Core Coverage: leaderboard
Metric: Formal core coverage (%, C5): union coverage of the design statements and signals in the formal core by the proven assertions on HierSVA-DS (342 hierarchical BaseJump STL modules, depths 0 to 9): static generation of SystemVerilog Assertions from RTL and submodule contracts, checked by formal proof in VC Formal; one run, reasoning enabled, temperature 0, strict JSON output. Source: arxiv.org. Saturation forecast: Around October 2027. 12 models tracked.
Top models
| # | Model | Score |
|---|---|---|
| 1 | Kimi K2.6 | 53.3 |
| 2 | GPT-5.5 | 51.4 |
| 3 | GLM-5.1 | 43.3 |
| 4 | Qwen 3.6 Max (Preview) (Thinking) | 37.7 |
| 5 | Claude Opus 4.7 (Thinking) | 34.7 |
| 6 | Gemini 3.1 Pro (Preview) | 33.8 |
| 7 | Claude Haiku 4.5 (Thinking) | 33.1 |
| 8 | Qwen 3.6 Plus (Thinking) | 29.4 |
| 9 | MiniMax-M2.7 | 26.5 |
| 10 | GPT-5 Mini | 14.5 |
Interactive version: theaggregate.ai/benchmark?slug=hiersva-b-formal-core-coverage · How It Works · Data refreshed daily, snapshot 2026-09-29.