HierSVA-B - Compile Rate: leaderboard

HierSVA-B (2026) benchmarks LLM-generated SystemVerilog assertions for hierarchical hardware formal verification on 342 BaseJump STL modules, checked by formal proof with a commercial tool. This board is the share of modules, in percent, whose generated assertion file compiles; higher is better.

Metric: Module compile rate (%, C1): share of the 342 modules whose generated assertion file compiles on HierSVA-DS (342 hierarchical BaseJump STL modules, depths 0 to 9): static generation of SystemVerilog Assertions from RTL and submodule contracts, checked by formal proof in VC Formal; one run, reasoning enabled, temperature 0, strict JSON output. Source: arxiv.org. Saturation forecast: Around February 2027. 12 models tracked.

Top models

#ModelScoreOverall rank
1Claude Opus 4.7 (Thinking)89.2#79 (Claude Opus 4.7)
2GPT-5.585.9#49
3Gemini 3.1 Pro (Preview)82.1#94
4GLM-5.176.9#179
5Qwen 3.6 Plus (Thinking)73.4#222 (Qwen 3.6 Plus)
6Qwen 3.6 Max (Preview) (Thinking)73.4
7Kimi K2.664.4#178
8Claude Haiku 4.5 (Thinking)58.1#568 (Claude Haiku 4.5)
9GPT-5 Mini55#348
10MiniMax-M2.718.8#518

No result here: #1 Claude Fable 5.2, #2 Gemini 4 Carbon, #5 Claude Opus 5.5.

Interactive version: theaggregate.ai/benchmark?slug=hiersva-b-compile-rate · How It Works · Data refreshed daily, snapshot 2026-11-13.