HierSVA-B - Compile Rate: leaderboard

Metric: Module compile rate (%, C1): share of the 342 modules whose generated assertion file compiles on HierSVA-DS (342 hierarchical BaseJump STL modules, depths 0 to 9): static generation of SystemVerilog Assertions from RTL and submodule contracts, checked by formal proof in VC Formal; one run, reasoning enabled, temperature 0, strict JSON output. Source: arxiv.org. Saturation forecast: Around December 2026. 12 models tracked.

Top models

#ModelScore
1Claude Opus 4.7 (Thinking)89.2
2GPT-5.585.9
3Gemini 3.1 Pro (Preview)82.1
4GLM-5.176.9
5Qwen 3.6 Max (Preview) (Thinking)73.4
6Qwen 3.6 Plus (Thinking)73.4
7Kimi K2.664.4
8Claude Haiku 4.5 (Thinking)58.1
9GPT-5 Mini55
10MiniMax-M2.718.8

Interactive version: theaggregate.ai/benchmark?slug=hiersva-b-compile-rate · How It Works · Data refreshed daily, snapshot 2026-09-29.